VHDL - 16:1 mux using 4:1 mux

VHDL module program:


1. Component - 4:1 mux:

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL;
entity mux4_1 is
    Port ( i : in  STD_LOGIC_VECTOR (3 downto 0);
           s : in  STD_LOGIC_VECTOR (1 downto 0);
           y : out  STD_LOGIC);
end mux4_1;
architecture Behavioral of mux4_1 is
begin
    with s select
 y<=  i(0) when "00",
  i(1) when "01",
  i(2) when "10",
  i(3) when others;

end Behavioral;

2. Main program for 16:1 mux:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;   
entity mux16_1 is
    Port ( i : in  STD_LOGIC_VECTOR (15 downto 0);
           s : in  STD_LOGIC_VECTOR (3 downto 0);
           o : out  STD_LOGIC);
end mux16_1;
architecture Behavioral of mux16_1 is
signal y1,y2,y3,y4 : std_logic;
  component mux4_1 is
    Port ( i : in  STD_LOGIC_VECTOR (3 downto 0);
           s : in  STD_LOGIC_VECTOR (1 downto 0);
           y : out  STD_LOGIC);
end component;
begin
  U1: mux4_1 port map (i(0)=>i(0),i(1)=>i(1),i(2)=>i(2),i(3)=>i(3),s(1)=>s(1),s(0)=>s(0),y=>y1);
  U2: mux4_1 port map (i(0)=>i(4),i(1)=>i(5),i(2)=>i(6),i(3)=>i(7),s(1)=>s(1),s(0)=>s(0),y=>y2);
  U3: mux4_1 port map (i(0)=>i(8),i(1)=>i(9),i(2)=>i(10),i(3)=>i(11),s(1)=>s(1),s(0)=>s(0),y=>y3);
  U4: mux4_1 port map (i(0)=>i(12),i(1)=>i(13),i(2)=>i(14),i(3)=>i(15),s(1)=>s(1),s(0)=>s(0),y=>y4);
  U5: mux4_1 port map (i(0)=>y1,i(1)=>y2,i(2)=>y3,i(3)=>y4,s(1)=>s(3),s(0)=>s(2),y=>o);
end Behavioral;

Register - Transfer - Level schematic:

VHDL Test bench program:

LIBRARY ieee;--MAIN
USE ieee.std_logic_1164.ALL;
 ENTITY mux16_11 IS
END mux16_11;
 ARCHITECTURE behavior OF mux16_11 IS 
     COMPONENT mux16_1
    PORT(
         i : IN  std_logic_vector(15 downto 0);
         s : IN  std_logic_vector(3 downto 0);
         o : OUT  std_logic
        );
    END COMPONENT;
      signal i : std_logic_vector(15 downto 0) := (others => '0');
   signal s : std_logic_vector(3 downto 0) := (others => '0');
   signal o : std_logic;
  BEGIN
    uut: mux16_1 PORT MAP (
          i => i,
          s => s,
          o => o
        );
stim_proc: process
   begin  
          wait for 100 ns; 
                             s<="1011";
   i<="1111110001010000";
   wait for 100 ns; 
   s<="1000";
   i<="1111110001010000";
   wait for 100 ns;
   s<="0110";
   i<="1111110001010000";
   wait for 100 ns;
      wait;
   end process;

END;

VHDL Test bench: